36-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Cypress Semiconductor Corporation • 198 Champion Court
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 10 of 31Truth TableThe truth table for the CY7C1416AV18, CY
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 11 of 31Write Cycle DescriptionsThe write cycle description
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 13 of 31IDCODEThe IDCODE instruction loads a vendor-specifi
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 14 of 31TAP Controller State DiagramThe state diagram for t
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 15 of 31TAP Controller Block DiagramTAP Electrical Characte
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 16 of 31TAP AC Switching Characteristics Over the Operating
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 17 of 31Identification Register Definitions Instruction Fie
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 18 of 31Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 19 of 31Power Up Sequence in DDR-II SRAMDDR-II SRAMs must b
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 2 of 31Logic Block Diagram (CY7C1416AV18)Logic Block Diagra
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 20 of 31Maximum RatingsExceeding maximum ratings may impair
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 21 of 31IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA,
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 22 of 31CapacitanceTested initially and after any design or
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 23 of 31Switching Characteristics Over the Operating Range
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 24 of 31Output TimestCOtCHQVC/C Clock Rise (or K/K in singl
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 25 of 31Switching WaveformsFigure 5. Read/Write/Deselect S
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 26 of 31Ordering Information Not all of the speed, package
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 27 of 31250 CY7C1416AV18-250BZC 51-85195 165-Ball Fine Pitc
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 28 of 31167 CY7C1416AV18-167BZC 51-85195 165-Ball Fine Pitc
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 29 of 31Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 3 of 31Logic Block Diagram (CY7C1418AV18)Logic Block Diagra
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 30 of 31Document History PageDocument Title: CY7C1416AV18,
Document Number: 38-05616 Rev. *F Revised January 29, 2009 Page 31 of 31DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress,
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 4 of 31Pin Configuration The pin configuration for CY7C1416
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 5 of 31CY7C1418AV18 (2M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 6 of 31Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]In
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 7 of 31CQ Output Clock CQ Referenced with Respect to C. Thi
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 8 of 31Functional OverviewThe CY7C1416AV18, CY7C1427AV18, C
CY7C1416AV18, CY7C1427AV18CY7C1418AV18, CY7C1420AV18Document Number: 38-05616 Rev. *F Page 9 of 31Depth ExpansionDepth expansion requires replicating
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