Cypress CY62146DV30 User Manual

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4-Mbit (256K x 16) Static RAM
CY62146DV30
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-05339 Rev. *A Revised February 2, 2005
Features
Very high speed: 45 ns
Wide voltage range: 2.20V–3.60V
Pin-compatible with CY62146CV30
Ultra-low active power
Typical active current: 1.5 mA @ f = 1 MHz
Typical active current: 8 mA @ f = f
max
Ultra low standby power
Easy memory expansion with CE
, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered 48-ball BGA and 44-pin TSOPII
Also available in Lead-free packages
Functional Description
[1]
The CY62146DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE
HIGH). The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE
HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE
, BLE HIGH),
or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62146DV30 is available in a 48-ball VFBGA, 44-pin
TSOPII packages.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
256K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
CE
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
10
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Summary of Contents

Page 1 - 4-Mbit (256K x 16) Static RAM

4-Mbit (256K x 16) Static RAMCY62146DV30Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600Document #: 38

Page 2

CY62146DV30Document #: 38-05339 Rev. *A Page 10 of 11© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to chang

Page 3

CY62146DV30Document #: 38-05339 Rev. *A Page 11 of 11Document History PageDocument Title:CY62146DV30 MoBL® 4-Mbit (256K x 16) Static RAMDocument Numb

Page 4

CY62146DV30Document #: 38-05339 Rev. *A Page 2 of 11 Notes: 2. NC pins are not internally connected on the die.3. DNU pins have to be left floating o

Page 5

CY62146DV30Document #: 38-05339 Rev. *A Page 3 of 11Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)St

Page 6

CY62146DV30Document #: 38-05339 Rev. *A Page 4 of 11 Capacitance (for all packages)[9]Parameter Description Test Conditions Max. UnitCINInput Capacit

Page 7

CY62146DV30Document #: 38-05339 Rev. *A Page 5 of 11Switching Characteristics Over the Operating Range[12]Parameter Description45 ns[10]55 ns 70 nsUn

Page 8

CY62146DV30Document #: 38-05339 Rev. *A Page 6 of 11Switching WaveformsRead Cycle 1 (Address Transition Controlled)[16, 17]Read Cycle No. 2 (OE Contr

Page 9

CY62146DV30Document #: 38-05339 Rev. *A Page 7 of 11Write Cycle No. 1 (WE Controlled)[15, 19, 20]Write Cycle No. 2 (CE Controlled)[15, 19, 20]Notes:

Page 10 - CY62146DV30

CY62146DV30Document #: 38-05339 Rev. *A Page 8 of 11Write Cycle No. 3 (WE Controlled, OE LOW)[20]Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20]Sw

Page 11

CY62146DV30Document #: 38-05339 Rev. *A Page 9 of 11Truth TableCE WE OE BHE BLE Inputs/Outputs Mode PowerH X X X X High Z Deselect/Power-Down Standby

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