Cypress CY7C1034DV33 User Manual

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Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-08351 Rev. *C Revised January 16, 2009
CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Features
High speed
t
AA
= 10 ns
Low active power
I
CC
= 175 mA at 10 ns
Low CMOS standby power
I
SB2
= 25 mA
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and CE
3
features
Available in Pb-free standard 119-Ball PBGA
Functional Description
The CY7C1034DV33 is a high performance CMOS static RAM
organized as 256K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE
1
LOW, CE
2
HIGH,
and CE
3
LOW) while forcing the Write Enable (WE) input LOW.
To read from the device, enable the chip by taking CE
1
LOW, CE
2
HIGH, and CE
3
LOW, while forcing the Output Enable (OE) LOW
and the Write Enable (WE
) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 IO pins (IO
0
to IO
23
) are placed in a high impedance state
when the device is deselected (CE
1
HIGH, CE
2
LOW, or CE
3
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE
1
LOW, CE
2
HIGH, CE
3
LOW, and WE LOW).
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K x 24
ARRAY
IO
0
– IO
23
OE
CE
1
, CE
2
, CE
3
WE
CONTROL LOGIC
Logic Block Diagram
A
(9:0)
A
(17:10)
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Summary of Contents

Page 1 - 6-Mbit (256K X 24) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Number: 001-08351 Rev. *C Revised January 16,

Page 2 - CY7C1034DV33

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 2 of 9 Selection GuideDescription –10 UnitMaximum Access Time 10 nsMaximum Operating Current 175

Page 3

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 3 of 9 Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These us

Page 4

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 4 of 9 Figure 2. AC Test Loads and Waveform [4]AC Switching Characteristics Over the operating r

Page 5

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 5 of 9 Write Cycle [9, 10]tWCWrite Cycle Time 10 nstSCECE Active LOW to Write End [3]7nstAWAddres

Page 6

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 6 of 9 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [13, 14]Fi

Page 7

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 7 of 9 Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]Figure 8. W

Page 8

CY7C1034DV33Document Number: 001-08351 Rev. *C Page 8 of 9 Ordering InformationSpeed(ns)Ordering CodePackage NamePackage TypeOperating Range10 CY7C10

Page 9

CY7C1034DV33© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconducto

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