36-Mbit DDR-II SIO SRAM 2-WordBurst ArchitectureCY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Cypress Semiconductor Corporation • 198 Champion C
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 10 of 30Truth TableThe truth table for CY7C1422BV18, CY7C1429BV
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 11 of 30Write Cycle DescriptionsThe write cycle description tab
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 12 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs inco
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 13 of 30IDCODEThe IDCODE instruction loads a vendor-specific, 3
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 14 of 30TAP Controller State DiagramThe state diagram for the T
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 15 of 30TAP Controller Block DiagramTAP Electrical Characterist
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 16 of 30TAP AC Switching Characteristics Over the Operating Ran
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 17 of 30Identification Register Definitions Instruction FieldVa
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 18 of 30Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # B
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 19 of 30Power Up Sequence in DDR-II SRAMDDR-II SRAMs must be po
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 2 of 30Logic Block Diagram (CY7C1422BV18)Logic Block Diagram (C
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 20 of 30Maximum RatingsExceeding maximum ratings may impair the
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 21 of 30IDD VDD Operating Supply VDD = Max,IOUT = 0 mA,f = fMAX
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 22 of 30CapacitanceTested initially and after any design or pro
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 23 of 30Switching Characteristics Over the Operating Range [20,
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 24 of 30Output TimestCOtCHQVC/C Clock Rise (or K/K in single cl
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 25 of 30Switching WaveformsFigure 5. Read/Write/Deselect Seque
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 26 of 30Ordering Information Not all of the speed, package and
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 27 of 30250 CY7C1422BV18-250BZC 51-85195 165-Ball Fine Pitch Ba
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 28 of 30167 CY7C1422BV18-167BZC 51-85195 165-Ball Fine Pitch Ba
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 29 of 30Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1.4 m
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 3 of 30Logic Block Diagram (CY7C1423BV18)Logic Block Diagram (C
Document #: 001-07035 Rev. *D Revised June 16, 2008 Page 30 of 30QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypre
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 4 of 30Pin Configuration The pin configuration for CY7C1422BV18
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 5 of 30CY7C1423BV18 (2M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC/144
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 6 of 30Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-S
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 7 of 30CQ Echo Clock CQ Referenced with Respect to C. This is a
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 8 of 30Functional OverviewThe CY7C1422BV18, CY7C1429BV18, CY7C1
CY7C1422BV18, CY7C1429BV18CY7C1423BV18, CY7C1424BV18Document #: 001-07035 Rev. *D Page 9 of 30Echo ClocksEcho clocks are provided on the DDR-II to sim
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