Cypress CY7C1462AV33 User Manual

36-Mbit (1M x 36/2M x 18/512K x 72)Pipelined SRAM with NoBL™ ArchitectureCY7C1460AV33CY7C1462AV33CY7C1464AV33Cypress Semiconductor Corporation • 198

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 10 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1460AV33/CY7C1462AV33/CY

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 11 of 27When the TAP controller is in the Capture-IR state, the twoleast signif

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 12 of 27When this scan cell, called the “extest output bus tri-state,” islatche

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 13 of 273.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 14 of 27Scan Register SizesRegister Name Bit Size (×36) Bit Size (×18) Bit Size

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 15 of 27165-ball FBGA Boundary Scan Order[13]CY7C1460AV33 (1M x 36), CY7C1462AV

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 16 of 27209-ball BGA Boundary Scan Order[13, 14]CY7C14604V33 (512K x 72)Bit# Ba

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 17 of 27Maximum Ratings (Above which the useful life may be impaired. For user

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 18 of 27 Note: 17. Tested initially and after any design or process changes tha

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 19 of 27Switching Characteristics Over the Operating Range[22, 23]Parameter Des

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 2 of 27 A0, A1, ACMODEBWaBWbWECE1CE2CE3OEREAD LOGICDQsDQPaDQPbDATASTEERINGOUTPU

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 20 of 27Switching Waveforms Read/Write/Timing[24, 25, 26]Notes: 24. For this wa

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 21 of 27Notes: 27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated C

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 22 of 27Ordering InformationNot all of the speed, package and temperature range

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 23 of 27250 CY7C1460AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 24 of 27Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION D

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 25 of 27Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 26 of 27© Cypress Semiconductor Corporation, 2006. The information contained he

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 27 of 27Document History PageDocument Title: CY7C1460AV33/CY7C1462AV33/CY7C1464

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 3 of 27Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 4 of 27Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPc

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 5 of 27Pin DefinitionsPin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAd

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 6 of 27CLK Input-ClockClock Input. Used to capture all synchronous inputs to th

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 7 of 27Functional OverviewThe CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 aresynchro

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 8 of 27counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h forCY7C1464AV3

CY7C1460AV33CY7C1462AV33CY7C1464AV33Document #: 38-05353 Rev. *D Page 9 of 27Write Cycle(Begin Burst)External L L L L L X L L-H Data In (D)Write Cycl