Cypress NoBL CY7C1471V25 User Manual download pdf (Page 8)

CY7C1471V25

CY7C1473V25

CY7C1475V25

Document #: 38-05287 Rev. *I Page 8 of 32

Pin Definitions

Name IO Description

, A

, A Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge

of the CLK. A

[1:0]

are fed to the two-bit burst counter.

, BW

Input-

Synchronous

Byte Write Inputs, Active LOW. Qualified with

WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK.

WE Input-

Synchronous

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous

Advance/Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN

is asserted LOW) the internal burst counter is advanced. When

LOW, a new address can be loaded into the device for an access. After being deselected,

ADV/LD must be driven LOW to load a new address.

CLK Input-

Clock

Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN

CLK is only recognized if CEN

is active LOW.

Input-

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE

and CE

to select or deselect the device.

Input-

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select or deselect the device.

Input-

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE

and

to select or deselect the device.

Input-

Asynchronous

Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic

block inside the device to control the direction of the IO pins. When LOW, the IO pins are

enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as

input data pins. OE

is masked during the data portion of a write sequence, during the first

clock when emerging from a deselected state, when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by

the SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN

does not deselect the device, CEN

can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous

ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull down.

IO-

Synchronous

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE

. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQ

and DQP

are placed in a tri-state condition.The

outputs are automatically tri-stated during the data portion of a write sequence, during the

first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE

DQP

IO-

Synchronous

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ

During

write sequences, DQP

is controlled by BW

correspondingly.

MODE Input Strap Pin Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V

or left floating selects

interleaved burst sequence.

Power Supply Power supply inputs to the core of the device.

DDQ

IO Power Supply Power supply for the IO circuitry.

Ground Ground for the device.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

JTAG feature is not used, this pin must be left unconnected. This pin is not available on

TQFP packages.

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Cypress NoBL CY7C1471V25 User Manual Page 8

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