Cypress CY7C1012DV33 User Manual

Browse online or download User Manual for Unknown Cypress CY7C1012DV33. Cypress CY7C1012DV33 User's Manual

  • Download
  • Add to my manuals
  • Print
  • Page
    / 11
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 0
Cypress Semiconductor Corporation 198 Champion Court San Jose
,
CA 95134-1709 408-943-2600
Document Number: 38-05610 Rev. *D Revised November 6, 2008
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
High speed
t
AA
= 10 ns
Low active power
I
CC
= 175 mA at 10 ns
Low CMOS standby power
I
SB2
= 25 mA
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Available in Pb-free standard 119-ball PBGA
Functional Description
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE
1
, CE
2
, and CE
3
).
CE
1
controls the data on the I/O
0
– I/O
7
, while CE
2
controls the
data on I/O
8
– I/O
15
, and CE
3
controls the data on the data pins
I/O
16
– I/O
23
. This device has an automatic power down feature
that significantly reduces power consumption when deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE
) input is LOW. Data on the respective input and output (I/O)
pins is then written into the location specified on the address pins
(A
0
– A
18
). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE
)
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE
) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (I/O) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 I/O pins (I/O
0
– I/O
23
) are placed in a high impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For more infor-
mation, see the Truth Table on page 8.
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
512K x 24
ARRAY
I/O
0
– I/O
7
OE
I/O
8
– I/O
15
CE
1
, CE
2
, CE
3
WE
I/O
16
– I/O
23
CONTROL LOGIC
A
(9:0)
A
(18:10)
[+] Feedback
Page view 0
1 2 3 4 5 6 ... 10 11

Summary of Contents

Page 1 - CY7C1012DV33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600Document Number: 38-05610 Rev. *D Revised November 6, 2

Page 2

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 10 of 11 Document History PageDocument Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM Document

Page 3

CY7C1012DV33© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconducto

Page 4

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 2 of 11 Selection GuideDescription –10 UnitMaximum Access Time 10 nsMaximum Operating Current 175

Page 5

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 3 of 11 Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These us

Page 6

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 4 of 11 CapacitanceTested initially and after any design or process changes that may affect these

Page 7

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 5 of 11 AC Switching CharacteristicsOver the Operating Range [5]Parameter Description–10UnitMin Ma

Page 8

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 6 of 11 Data Retention CharacteristicsOver the Operating RangeParameter Description Conditions [3]

Page 9

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 7 of 11 Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17]Figure 6. Write Cycle No. 2 (WE C

Page 10

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 8 of 11 Truth TableCE1CE2CE3OE WE I/O0 – I/O7 I/O8 – I/O15 I/O16 – I/O23 Mode PowerH H H X X Hi

Page 11

CY7C1012DV33Document Number: 38-05610 Rev. *D Page 9 of 11 Ordering InformationSpeed (ns)Ordering CodePackage NamePackage TypeOperating Range10 CY7C1

Comments to this Manuals

No comments