Cypress NoBL CY7C1470BV25 User Manual

72-Mbit (2M x 36/4M x 18/1M x 72)Pipelined SRAM with NoBL™ ArchitectureCY7C1470BV25CY7C1472BV25, CY7C1474BV25Cypress Semiconductor Corporation • 198 C

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 10 of 29Table 4. Truth TableThe truth table for CY7C1470BV25, CY7C1472BV25,

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 11 of 29Table 5. Partial Write Cycle DescriptionThe partial write cycle desc

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 12 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1470BV25, CY7C1472BV25

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 13 of 29Instruction RegisterThree-bit instructions can be serially loaded int

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 14 of 29possible to capture all other signals and simply ignore the valueof t

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 15 of 29TAP AC Switching Characteristics Over the Operating Range [9, 10]Para

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 16 of 292.5V TAP AC Test ConditionsInput pulse levels...

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 17 of 29Table 8. Identification CodesInstruction Code DescriptionEXTEST 000

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 18 of 29Boundary Scan Exit Order (4M x 18)Bit # 165-Ball ID Bit # 165-Ball ID

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 19 of 29Maximum Ratings Exceeding maximum ratings may impair the useful life

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 2 of 29Logic Block Diagram – CY7C1470BV25 (2M x 36)Logic Block Diagram – CY7C

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 20 of 29ISB3Automatic CE Power Down Current—CMOS InputsMax. VDD, Device Desel

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 21 of 29Switching Characteristics Over the Operating Range. Timing reference

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 22 of 29Switching Waveforms Figure 6 shows read-write timing waveform.[19, 20

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 23 of 29Figure 7 shows NOP, STALL and DESELECT Cycles waveform.[19, 20, 22]Fi

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 24 of 29Ordering InformationNot all of the speed, package and temperature ran

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 25 of 29250 CY7C1470BV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 26 of 29Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack (14 x

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 27 of 29Figure 10. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165Package Diagram

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 28 of 29Figure 11. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167Package Diagra

Document #: 001-15032 Rev. *D Revised February 29, 2008 Page 29 of 29NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 3 of 29Logic Block Diagram – CY7C1474BV25 (1M x 72)A0, A1, ACMODECE1CE2CE3OER

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 4 of 29Pin Configurations AAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb D

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 5 of 29Pin Configurations (continued)165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 6 of 29Pin Configurations (continued)CY7C1474BV25 (1M × 72)209-Ball FBGA (14

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 7 of 29Table 1. Pin DefinitionsPin Name IO Type Pin DescriptionA0A1AInput-Sy

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 8 of 29Functional OverviewThe CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25are

CY7C1470BV25CY7C1472BV25, CY7C1474BV25Document #: 001-15032 Rev. *D Page 9 of 29access (read, write, or deselect) is latched into the AddressRegister