Cypress CY7C1383DV25 User Manual
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18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05547 Rev. *E Revised Feburary 14, 2007
Features
• Supports 133 MHz bus operations
• 512K x 36/1M x 18 common IO
• 2.5V core power supply (V
DD
)
• 2.5V IO supply (V
DDQ
)
• Fast clock-to-output times, 6.5 ns (133 MHz version)
• Provides high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1381DV25/CY7C1383DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1381FV25/CY7C1383FV25 available in Pb-free and
non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
Functional Description
[1]
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in
a burst and increments the address automatically for the rest
of the burst access. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE
1
), depth expansion
chip enables (CE
2
and
CE
3
[2]
), burst control inputs (ADSC,
ADSP, and ADV), write enables
(
BW
x
, and BWE), and global
write (GW
). Asynchronous inputs include the output enable
(OE) and the ZZ pin.
The
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25
allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe
(ADSP
) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP
) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV
).
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 operates from a +2.5V core power supply
while all outputs also operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 210 175 mA
Maximum CMOS Standby Current 70 70 mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
3,
CE
2
are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.
[+] Feedback
Summary of Contents
Page 1 - CY7C1383DV25, CY7C1383FV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAMCY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Cypress Semiconductor Corporation • 198 Champion Cour
Page 2 - (1M x 18)
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 10 of 28Truth Table for Read/Write [4, 9]Function (CY7C1381DV25/
Page 3 - Pin Configurations
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 11 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1381DV25/
Page 4 - CY7C1381FV25 (512K x 36)
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 12 of 28When the TAP controller is in the Capture-IR state, the
Page 5 - CY7C1383DV25 (1Mx 18)
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 13 of 28the TAP controller, it will directly control the state o
Page 6
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 14 of 282.5V TAP AC Test ConditionsInput pulse levels ...
Page 7
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 15 of 28Identification CodesInstruction Code DescriptionEXTEST 0
Page 8
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 16 of 28165-Ball BGA Boundary Scan Order[13, 15] Bit # Ball ID B
Page 9
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 17 of 28Maximum RatingsExceeding the maximum ratings may impair
Page 10
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 18 of 28Capacitance [18]Parameter Description Test Conditions100
Page 11 - TAP Controller Block Diagram
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 19 of 28Switching CharacteristicsOver the Operating Range[19, 20
Page 12
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 2 of 28Logic Block Diagram – CY7C1381DV25/CY7C1381FV25 [3] (512K
Page 13
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 20 of 28Timing DiagramsRead Cycle Timing [25]tCYCtCLCLKtADHtADSA
Page 14
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 21 of 28 Write Cycle Timing [25, 26]Timing Diagrams (continued)t
Page 15
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 22 of 28Read/Write Cycle Timing [25, 27, 28]Timing Diagrams (con
Page 16
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 23 of 28ZZ Mode Timing [29, 30]Timing Diagrams (continued)tZZISU
Page 17
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 24 of 28Ordering InformationNot all of the speed, package, and t
Page 18
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 25 of 28Package DiagramsFigure 1. 100-Pin Thin Plastic Quad Flat
Page 19
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 26 of 28Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)Pack
Page 20
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 27 of 28© Cypress Semiconductor Corporation, 2006-2007. The info
Page 21
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 28 of 28Document History PageDocument Title: CY7C1381DV25/CY7C13
Page 22
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 3 of 28Pin ConfigurationsAAAAA1A0NCNCVSSVDDAAAAAAAADQPBDQBDQBVDD
Page 23
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 4 of 28Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDD
Page 24
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 5 of 28Pin Configurations (continued)165-Ball FBGA Pinout (3 Chi
Page 25
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 6 of 28Pin DefinitionsName IO DescriptionA0, A1, A Input-Synchro
Page 26
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 7 of 28Functional OverviewAll synchronous inputs pass through in
Page 27
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 8 of 28and the IOs must be tri-stated prior to the presentation
Page 28
CY7C1381DV25, CY7C1381FV25CY7C1383DV25, CY7C1383FV25Document #: 38-05547 Rev. *E Page 9 of 28Truth Table [4, 5, 6, 7, 8]Cycle DescriptionAddress UsedC
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