CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V1836-Mbit DDR-II+ SRAM 2-WordBurst Architecture (2.5 Cycle Read Latency)Cypress Semiconductor Corporatio
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 10 of 27Write Cycle Descriptions The write cycle description
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 11 of 27Write Cycle Descriptions The write cycle description
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 12 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs in
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 13 of 27IDCODEThe IDCODE instruction loads a vendor-specific,
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 14 of 27TAP Controller State DiagramThe state diagram for the
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 15 of 27TAP Controller Block DiagramTAP Electrical Characteri
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 16 of 27TAP AC Switching Characteristics Over the Operating R
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 17 of 27Identification Register Definitions Instruction Field
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 18 of 27Boundary Scan OrderBit # Bump ID Bit # Bump ID Bit #
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 19 of 27Power Up Sequence in DDR-II+ SRAMDDR-II+ SRAMs must b
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 2 of 27Logic Block Diagram (CY7C1266V18)Logic Block Diagram (
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 20 of 27Maximum Ratings Exceeding maximum ratings may impair
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 21 of 27Capacitance[20]Parameter Description Test Conditions
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 22 of 27Switching Characteristics Over the Operating Range[21
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 23 of 27Switching WaveformsRead/Write/Deselect Sequence[29, 3
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 24 of 27Ordering Information Not all of the speed, package an
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 25 of 27333 CY7C1266V18-333BZC 51-85195 165-ball Fine Pitch B
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 26 of 27Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1.4
Document Number: 001-06347 Rev. *D Revised March 11, 2008 Page 27 of 27All product and company names mentioned in this document are the trademarks of
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 3 of 27Logic Block Diagram (CY7C1268V18)Logic Block Diagram (
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 4 of 27Pin ConfigurationsCY7C1266V18 (4M x 8)165-Ball FBGA (1
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 5 of 27Pin Configurations (continued)CY7C1268V18 (2M x 18)165
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 6 of 27Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]Inpu
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 7 of 27ZQ Input Output Impedance Matching Input. This input i
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 8 of 27Functional OverviewThe CY7C1266V18, CY7C1277V18, CY7C1
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 9 of 27Delay Lock Loop (DLL)These chips use a DLL that is des
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