Cypress CY7C028V User Manual download pdf

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

3.3V 32K/64K x 16/18 Dual-Port Static

RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-06078 Rev. *B Revised December 09, 2008

Features

■

True Dual-Ported memory cells which allow

simultaneous access of the same memory location

■

32K x 16 organization (CY7C027V/027VN/027AV

[1]

)

■

64K x 16 organization (CY7C028V)

■

32K x 18 organization (CY7C037V/037AV

[2]

)

■

64K x 18 organization (CY7C038V)

■

0.35 micron CMOS for optimum speed and power

■

High speed access: 15, 20, and 25 ns

■

Low operating power

■

Active: I

= 115 mA (typical)

■

Standby: I

SB3

= 10 μA (typical)

■

Fully asynchronous operation

■

Automatic power down

■

Expandable data bus to 32/36 bits or more using Master/Slave

chip select when using more than one device

■

On-chip arbitration logic

■

Semaphores included to permit software handshaking

between ports

■

INT flag for port-to-port communication

■

Separate upper-byte and lower-byte control

■

Dual chip enables

■

Pin select for Master or Slave

■

Commercial and Industrial temperature ranges

■

100-pin Pb-free TQFP and 100-pin TQFP

Notes

1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.

2. CY7C037V and CY7C037AV are functionally identical.

3. I/O

–I/O

for x16 devices; I/O

–I/O

for x18 devices.

4. I/O

–I/O

for x16 devices; I/O

–I/O

for x18 devices.

5. A

–A

for 32K; A

–A

for 64K devices.

6. BUSY

is an output in master mode and an input in slave mode.

R/W

I/O

8/9L

–I/O

15/17L

I/O

Control

Address

Decode

–A

14/15L

R/W

BUSY

I/O

Control

Interrupt

Semaphore

Arbitration

SEM

INT

M/S

I/O

–I/O

7/8L

R/W

I/O

8/9L

–I/O

15/17R

I/O

–I/O

7/8R

Logic Block Diagram

–A

14/15L

True Dual-Ported

RAM Array

–A

14/15R

R/W

BUSY

SEM

INT

Address

Decode

–A

14/15R

[3]

[4]

[5]

[6]

[5] [5]

15/16

8/9

15/16

8/9

15/16 15/16

[+] Feedback

1 2 3 4 5 6 ... 17 18

Summary of Contents

Page 1 - CY7C037V/037AV/038V

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038V3.3V 32K/64K x 16/18 Dual-Port StaticRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose,

Page 2 - CY7C028V (64K x 16)

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 10 of 18Notes20. R/W must be HIGH during all address transitions.21. A w

Page 3 - CY7C038V (64K x 18)

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 11 of 18Notes29. CE = HIGH for the duration of the above timing (both wr

Page 4

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 12 of 18Note33. CEL = CER = LOW.Switching Waveforms(continued)VALIDtDDDt

Page 5

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 13 of 18Note34. If tPS is violated, the busy signal is asserted on one s

Page 6

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 14 of 18Figure 15. Interrupt Timing DiagramsNotes35. tHA depends on whi

Page 7

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 15 of 18 Table 1. Non-Contending Read/WriteInputs OutputsCE R/W OE UB LB

Page 8

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 16 of 18Ordering Information32K x16 3.3V Asynchronous Dual-Port SRAMSpee

Page 9

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 17 of 18Package DiagramFigure 16. 100-Pin Pb-Free Thin Plastic Quad Fla

Page 10

Document #: 38-06078 Rev. *B Revised December 09, 2008 Page 18 of 18All products and company names mentioned in this document may be the trademarks of

Page 11

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 2 of 18Pin ConfigurationsFigure 1. 100-Pin TQFP (Top View)13292 91 90 8

Page 12

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 3 of 18Pin Configurations (continued)Figure 2. 100-Pin TQFP (Top View)1

Page 13

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 4 of 18ArchitectureThe CY7C027V/027VN/027AV/028V andCY7037V/037AV/038V c

Page 14

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 5 of 18generated to the owner. The interrupt is reset when the ownerread

Page 15

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 6 of 18Maximum RatingsExceeding maximum ratings may shorten the useful l

Page 16

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 7 of 18Figure 3. AC Test Loads and Waveforms3.0VGND90%90%10%3ns3ns10%AL

Page 17

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 8 of 18Data Retention ModeThe CY7C027V/027VN/027AV/028V andCY7037V/037AV

Page 18

CY7C027V/027VN/027AV/028VCY7C037V/037AV/038VDocument #: 38-06078 Rev. *B Page 9 of 18Switching WaveformsNotes15. R/W is HIGH for read cycles.16. Devic

Related models: CY7C037V | CY7C038V | CY7C027AV | CY7C027V |

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Cypress CY7C028V User Manual

Browse online or download User Manual for Hardware Cypress CY7C028V. Cypress CY7C028V User Manual

Summary of Contents

Related models: CY7C037V | CY7C038V | CY7C027AV | CY7C027V |

Comments to this Manuals

Related products and manuals for Hardware Cypress CY7C028V