Cypress CY7C1446AV33 User Manual

36-Mbit (1M x 36/2M x 18/512K x 72)Pipelined Sync SRAMCY7C1440AV33CY7C1442AV33CY7C1446AV33Cypress Semiconductor Corporation • 198 Champion Court • S

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 10 of 31READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-StateREAD C

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 11 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1440AV33/CY7C1442AV33/CY

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 12 of 31Performing a TAP ResetA RESET is performed by forcing TMS HIGH (VDD) fo

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 13 of 31The shifting of data for the SAMPLE and PRELOAD phasescan occur concurr

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 14 of 313.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 15 of 31 TAP DC Electrical Characteristics And Operating Conditions (0°C <

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 16 of 31 Notes: 14. Balls that are NC (No Connect) are preset LOW.15. Bit# 89 i

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 17 of 31 Note: 16. Bit# 138 is preset HIGH.209-ball FBGA Boundary Scan Order [1

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 18 of 31Maximum Ratings(Above which the useful life may be impaired. For user g

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 19 of 31Capacitance[19]Parameter Description Test Conditions100 TQFPMax.165 FBG

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 2 of 31Logic Block Diagram – CY7C1440AV33 (1M x 36)ADDRESSREGISTERADVCLKBURSTCO

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 20 of 31Switching Characteristics Over the Operating Range[24, 25]Parameter Des

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 21 of 31Switching WaveformsRead Cycle Timing[26]Note: 26. On this diagram, when

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 22 of 31Write Cycle Timing[26, 27]Note: 27.Full width write can be initiated by

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 23 of 31Read/Write Cycle Timing[26, 28, 29]Notes: 28. The data bus (Q) remains

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 24 of 31ZZ Mode Timing[30, 31]Notes: 30. Device must be deselected when enterin

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 25 of 31Ordering InformationNot all of the speed, package and temperature range

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 26 of 31250 CY7C1440AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 27 of 31Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 28 of 31Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 29 of 31© Cypress Semiconductor Corporation, 2006. The information contained he

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 3 of 31BWDBWCBWBBWABWEGWCE1CE2CE3OEENABLEREGISTERPIPELINEDENABLEADDRESSREGISTER

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 30 of 31Document History PageDocument Title: CY7C1440AV33/CY7C1442AV33/CY7C1446

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 31 of 31*E 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VD

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 4 of 31Pin Configurations DQPBDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQVDDQDQBDQBVSSNCVDDZ

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 5 of 31Pin Configurations (continued)165-ball FBGA (15 x 17 x 1.4 mm) Pinout C

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 6 of 31209-ball FBGA (14 x 22 x 1.76 mm) PinoutCY7C1446AV33 (512K × 72)Pin Conf

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 7 of 31CE2Input-SynchronousChip Enable 2 Input, active HIGH. Sampled on the ris

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 8 of 31Functional OverviewAll synchronous inputs pass through input registers c

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 9 of 31 Interleaved Burst Address Table (MODE = Floating or VDD)FirstAddressA1