Cypress ISR 37000 CPLD User Manual download pdf (Page 17)

Ultra37000 CPLD Family

Document #: 38-03007 Rev. *E Page 17 of 64

Parameter

[11]

Output Waveform—Measurement Level

ER(–)

1.5V

ER(+)

2.6V

EA(+)

1.5V

EA(–)

the

(d) Test Waveforms

0.5V

Switching Characteristics Over the Operating Range

[12]

Parameter Description Unit

Combinatorial Mode Parameters

[13, 14, 15]

Input to Combinatorial Output ns

PDL

[13, 14, 15]

Input to Output Through Transparent Input or Output Latch ns

PDLL

[13, 14, 15]

Input to Output Through Transparent Input and Output Latches ns

[13, 14, 15]

Input to Output Enable ns

[11, 13]

Input to Output Disable ns

Input Register Parameters

Clock or Latch Enable Input LOW Time

[8]

Clock or Latch Enable Input HIGH Time

[8]

Input Register or Latch Set-up Time ns

Input Register or Latch Hold Time ns

ICO

[13, 14, 15]

Input Register Clock or Latch Enable to Combinatorial Output ns

ICOL

[13, 14, 15]

Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns

Synchronous Clocking Parameters

[14, 15]

Synchronous Clock (CLK

, CLK

, or CLK

) or Latch Enable to Output ns

[13]

Set-Up Time from Input to Sync. Clk (CLK

, CLK

, or CLK

) or Latch Enable ns

CO2

[13, 14, 15]

Output Synchronous Clock (CLK

, CLK

, or CLK

) or Latch Enable to Combinatorial Output

Delay (Through Logic Array)

SCS

[13]

Output Synchronous Clock (CLK

, CLK

, or CLK

) or Latch Enable to Output Synchronous

Clock (CLK

, CLK

, or CLK

) or Latch Enable (Through Logic Array)

[13]

Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK

CLK

, CLK

, or CLK

) or Latch Enable

Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK

CLK

, CLK

, or CLK

) or Latch Enable

Notes:

11. t

measured with 5-pF AC Test Load and t

measured with 35-pF AC Test Load.

12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.

13. Logic Blocks operating in Low-Power Mode, add t

to this spec.

14. Outputs using Slow Output Slew Rate, add t

SLEW

to this spec.

15. When V

CCO

= 3.3V, add t

3.3IO

to this spec.

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